Flash Memory Device

ABSTRACT

A flash memory device including a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a division of U.S. application Ser. No. 12/607,183 filed Oct.28, 2009, which claims the priority benefit under USC 119 of KR10-2009-0005062 filed on Jan. 21, 2009, the entire respectivedisclosures of which are incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present disclosure is directed to a flash memory device and a methodof manufacturing the same. More particularly, the present disclosure isdirected to a flash memory device having contact holes formed in adielectric layer, and a method of manufacturing the same.

2. Brief Description of Related Technology

The cell array of a flash memory device includes a string structure. Thestring structure includes a drain select transistor having a draincoupled to a bit line, a source select transistor having a sourcecoupled to a common source line, and a number of memory cells coupled inseries between the drain select transistor and the source selecttransistor. A number of the string structures are formed in parallel andare electrically isolated from each other by an isolation layer.Furthermore, each of the drain select transistor, the source selecttransistor, and the memory cell includes a gate having a stack-typestructure in which a floating gate, a dielectric layer, and a controlgate are stacked. In the string structures formed in parallel, thecontrol gates of the drain select transistors are interconnected to forma drain select line, the control gates of the source select transistorsare interconnected to form a source select line, and the control gatesof the memory cells are interconnected to form a word line. On the otherhand, the floating gates of the source and drain select transistors areelectrically coupled to the control gates of the source and drain selecttransistors through contact holes formed in the dielectric layers. Thatis, the source select line and the drain select line are electricallycoupled to the underlying floating gates of the source and drain selecttransistors through the contact holes formed in the dielectric layers.

A prior art method of forming the contact holes in the dielectric layersis described in detail below.

First, a gate insulating layer, a conductive layer for the floatinggates, and an isolation hard mask pattern are formed over asemiconductor substrate. The conductive layer for the floating gates,the gate insulating layer, and the semiconductor substrate are etched byan etch process using the isolation hard mask pattern as an etchbarrier. Trenches are formed in portions in which the semiconductorsubstrate has been etched, and active regions are defined in regions onthe semiconductor substrate parallel to the trenches. Thus, theconductive layer for the floating gates and the gate insulating layerremain on the active regions.

After the trenches are formed, the trenches are gap-filled with aninsulation material, and the conductive layer for the floating gates isexposed by a polishing process. Accordingly, the insulation materialremains within the trenches to thereby form isolation layers, and theactive regions are defined in regions on the semiconductor substrateparallel to the isolation layers. The isolation layer is formed to havea lower surface height than the surface of the conductive layer for thefloating gates by controlling the effective field height (EFH).Consequently, a stepped topology is formed on a surface of thesemiconductor substrate, including the isolation layer and theconductive layer for the floating gates.

The dielectric layer is formed on the surface of the semiconductorsubstrate having the stepped topology, including the isolation layer andthe conductive layer for the floating gates. The surface of thedielectric layer also has a stepped topology because the dielectriclayer is formed on the surface of the semiconductor substrate having thestepped topology (see FIG. 1). Thus, if auxiliary layers, such as acapping layer and a bottom anti-reflective coating (BARC) layer, arestacked over the dielectric layer in a subsequent process, the thicknessof the auxiliary layers is thicker on the isolation region than on theactive region.

In the state in which the thickness of the auxiliary layers is notuniform as described above, a photoresist pattern is formed over theauxiliary layers. The photoresist pattern is used as a pattern whichdefines regions where the contact holes will be formed. The contactholes are formed in the dielectric layer by etching the auxiliary layersand the dielectric layer using an etch process using the photoresistpattern as an etch barrier. When the contact holes are formed in thedielectric layer, the thickness of layers (i.e., etch targets) is notuniform because of the stepped topology previously described, therebymaking it difficult to secure a reasonable margin of error for the etchprocess. Consequently, the contact holes may not be formed in part ofthe dielectric layer, and a connection failure may occur between theselect lines and the conductive layer for the floating gates.Furthermore, in the process of etching the auxiliary layers when thecontact holes are formed in the dielectric layer, it is difficult tocontrol the etch targets. Accordingly, there is a limit to an increasein the contact area.

FIG. 1 is a section view illustrating a process of forming contact holesin a dielectric layer. In FIG. 1, regions where the contact holes (notshown) are formed intersecting isolation layers.

Referring to FIG. 1, steps are formed on the entire surface of asemiconductor substrate 11 as a result of the isolation layers 17. Thus,when forming the contact holes in the dielectric layer 19, portions ofan auxiliary layer 21 over a conductive layer 15 for the floating gatesare exposed and removed earlier than portions of the auxiliary layer 21over the isolation layers 17. On the other hand, in order to improve thecontact resistance of the conductive layer 15 for floating gates and asource select line or a drain select line which is formed later, acontact area of the conductive layer 15 for floating gates and thesource select line or the drain select line must be widened. To thisend, portions of the auxiliary layer 21 exposed over the isolationlayers 17 have to be removed so that the sidewalls of the conductivelayer 15 for the floating gates are exposed. However, when controllingthe EFH, the height of the isolation layer 17 is lowered, which makesthe auxiliary layer 21 over the isolation layer 17 close to a gateinsulating layer 13. Accordingly, it is difficult to control the etchthickness of the auxiliary layer 21 without damaging the gate insulatinglayer 13, and also there is a limit to an increase in the contact area.

BRIEF SUMMARY

Embodiments of the present disclosure are directed to a method ofmanufacturing a flash memory device which can improve an etch margin oferror in a process of forming contact holes in a dielectric layer andcan also increase a contact area of a select line and a floating gate.

A flash memory device according to an embodiment of the presentdisclosure includes a semiconductor substrate that includes selectiontransistor regions and a memory cell region defined between theselection transistor regions, first isolation layers formed in theselection transistor regions, and second isolation layers formed in thememory cell region, wherein the second isolation layers have a lowerheight than the first isolation layers.

A flash memory device according to another embodiment of the presentdisclosure includes a semiconductor substrate that includes selectiontransistor regions and a memory cell region defined between theselection transistor regions, a gate insulating layer formed on thesemiconductor substrate, and a conductive layer formed on the gateinsulating layer, the conductive layer having first conductive layersdisposed in the selection transistor regions and second conductivelayers disposed in the memory cell region, the first conductive layersbeing recessed and having concave top surfaces.

The first conductive layers can be separated from each other by firstisolation layers interposed between adjacent first conductive layers.The second conductive layers can be separated from each other by secondisolation layers interposed between adjacent second conductive layers.The second isolation layers can have a lower higher than the firstisolation layers.

A method of manufacturing a flash memory device according to anembodiment of the present disclosure includes providing a semiconductorsubstrate that includes selection transistor regions and a memory cellregion defined between the selection transistor regions, and formingfirst isolation layers in the selection transistor regions and formingsecond isolation layers having a lower height than the first isolationlayers in the memory cell region.

The selection transistor regions comprise a source selection transistorregion and a drain selection transistor region. The memory cell regionis defined between the source selection transistor region and the drainselection transistor region.

The first isolation layers and the second isolation layers can beadjacent and coupled to each other.

The first isolation layers in the selection transistor regions and thesecond isolation layers having a lower height than the first isolationlayers in the memory cell region can be formed by forming the first andsecond isolation layers to a same height, forming a first photoresistpattern configured to cover the first isolation layers and to expose thesecond isolation layers, lowering the height of the second isolationlayers by performing an etch process using the first photoresist patternas an etch barrier, and removing the first photoresist pattern.

The semiconductor substrate can further include a peripheral region.Third isolation layers having a same height as the first and secondisolation layers can also be formed in the peripheral region whenforming the first and second isolation layers to the same height. Thefirst photoresist pattern can also be formed to further cover the thirdisolation layer.

The first and second isolation layers can be formed to the same heightby stacking a gate insulating layer and a conductive layer over thesemiconductor substrate, forming trenches by etching the conductivelayer, the gate insulating layer, and the semiconductor substrate,thereby forming the first and second conductive layers, and gap-fillingthe trenches with an insulation material, and polishing a surface of theinsulation material to expose the first and second conductive layer.

After the first photoresist pattern is removed, the height of the firstand second isolation layers remains higher than the height of the gateinsulating layer.

After the first photoresist pattern is removed, a dielectric layer canbe formed over the semiconductor substrate, including the first andsecond isolation layers and the first and second conductive layers. Thedielectric layer can be etched to expose the first conductive layers andthe first isolation layers formed in the selection transistor regions.Select lines which contact the first conductive layers and the firstisolation layers formed in the selection transistor regions and wordlines which contact the dielectric layer formed in the memory cellregion are formed.

After the dielectric layer is formed, a capping layer can be formed onthe dielectric layer using, for example, polysilicon, a secondphotoresist pattern is formed over the capping layer, and the cappinglayer is etched by an etch process using the second photoresist patternas an etch barrier.

The capping layer can be etched, for example, using an etch gascomprising HBr gas and O₂ gas.

After the dielectric layer is etched, the height of the first isolationlayers remains higher than the height of the gate insulating layer. Theheight of the first isolation layers can be lowered and can become lowerthan the height of the first conductive layers.

The lowering of the height of the first isolation layer can be performedby a cleaning process using, for example, a hydrofluoric acid (HF)solution.

After the dielectric layer is etched, the height of the first isolationlayers can becomes lower than the height of the first conductive layers.A cleaning process can be performed such that the height of the firstisolation layers remains higher than the height of the gate insulatinglayer.

The cleaning process is performed using a hydrofluoric acid (HF)solution.

The select lines can contact a top surface and sidewalls of the firstconductive layers.

After the dielectric layer is etched, surfaces of each of the firstconductive layers disposed in the selection transistor regions can berecessed.

The recessing of the surfaces of the first conductive layers can beperformed, for example, using an etch gas comprising HBr gas and N2 gas.

The recessing of the surfaces of the conductive layer can also beperformed, for example, by applying a bias power that is lower than abias power applied when the dielectric layer is etched.

A method of manufacturing a flash memory device according to anembodiment of the present disclosure can include providing asemiconductor substrate that includes selection transistor regions and amemory cell region defined between the selection transistor regions,stacking a gate insulating layer and a conductive layer over thesemiconductor substrate, wherein the conductive layer comprises firstconductive layers disposed in the selection transistor regions andsecond conductive layers disposed in the memory cell region, andrecessing surfaces of each of the first conductive layers so that thefirst conductive layers have concave top surfaces.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a prior art process of formingcontact holes in a dielectric layer;

FIG. 2 is a layout diagram illustrating a flash memory device accordingto an embodiment;

FIGS. 3A to 3F are sectional views sequentially showing a method ofmanufacturing the flash memory device in the direction of line I-I′ andII-II′ shown in FIG. 2; and

FIGS. 4A to 4F are sectional views illustrating a peripheral regiondefined outside a memory cell region and selection transistor regions.

DESCRIPTION OF EMBODIMENTS

Hereinafter, the present disclosure will be described in detail inconnection with embodiments with reference to the accompanying drawings.The drawing figures are provided to allow those having ordinary skill inthe art to understand the scope of the embodiments of the disclosure,and are not intended to be limiting.

FIG. 2 is a layout diagram illustrating a flash memory device accordingto an embodiment of the present disclosure. The cell array of the flashmemory device includes a string structure. The string structure includesa drain select transistor having a drain coupled to a bit line, a sourceselect transistor having a source coupled to a common source line, and anumber of memory cells coupled in series between the drain selecttransistor and the source select transistor. A number of the stringstructures are formed in parallel and are electrically isolated fromeach other on the basis of an isolation layer. The source selecttransistor SST and the drain select transistor DST are formed in theselection transistor regions of the semiconductor substrate, and thememory cells are formed in the memory cell regions of the semiconductorsubstrate. The selection transistor regions include a source selectiontransistor (SST) region and a drain selection transistor (DST) region.The memory cell region is defined between the SST region and the DSTregion.

The memory cell region and the selection transistor regions includeisolation regions B and active regions A, which are alternately definedin parallel to each other.

Furthermore, select lines are formed in the selection transistor region,and a number of word lines WL are formed in the memory cell region. Theselect lines include a drain select line DSL formed in the DST regionand a source select line SSL formed in the SST region.

FIGS. 3A to 3F are sectional views sequentially showing a method ofmanufacturing the flash memory device in the direction of lines I-I′ andII-II′ shown in FIG. 2. The sectional view taken along line I-I′corresponds to the SST region of the selection transistor regions, butis identical to the sectional view of the DST region taken in the samedirection as line I-I′. Accordingly, the sectional view taken along lineI-I′ corresponds to the sectional view of the selection transistorregions. The sectional view taken along line II-II′ corresponds to thesectional view of the memory cell region.

Referring to FIGS. 2 and 3A, there is provided the semiconductorsubstrate 101, including the selection transistor regions and the memorycell region defined between the selection transistor regions. Each ofthe selection transistor region and the memory cell region includes theactive regions A and the isolation regions B, which are alternatelydefined in parallel to each other. A gate insulating layer 103 and aconductive layer are stacked over the active regions A of thesemiconductor substrate 101. The conductive layer includes firstconductive layers 105 a disposed in the selection transistor regions andthe second conductive layers 105 b disposed in the memory cell region.It will be understood that the term conductive layer can refer bothindividually and collectively to the conductive layer elements. Thus, itwill be understood that the term “first conductive layers 105 a” canrefer to the conductive layer elements disposed in the selectiontransistor regions and separated by the isolation regions B of theselection transistor regions, and the term “second conductive layers 105b” can refer to the conductive layer elements disposed in the memorycell region and separated by the isolation regions B of the memory cellregion. First isolation layers 107 a are formed in the isolation regionsB of the selection transistor regions, and second isolation layers 107 bare formed in the respective isolation regions B of the memory cellregion. It will be understood that the term isolation layer can referboth individually and collectively to the isolation layer elements.Thus, it will be understood that the term “first isolation layers 107 a”can refer to the isolation layer elements disposed in the isolationregions B of the selection transistor regions, and the term “secondisolation layers 107 b” can refer to the isolation layer elementsdisposed in the isolation regions B of the memory cell region. The firstisolation layers 107 a and the second isolation layers 107 b areadjacent to and connected to each other. A method of stacking the gateinsulating layer 103 and the first and second conductive layers 105 aand 105 b over the active regions A and forming the first or secondisolation layers 107 a and 107 b in the isolation regions B is describedin detail below.

The gate insulating layer 103 and the conductive layer which is used toform the first and second conductive layers 105 a and 105 b are stackedover the semiconductor substrate 101. An isolation hard mask pattern(not shown) is formed on the conductive layer. The gate insulating layer103 can be formed, for example, using an oxide layer, and the conductivelayer (i.e., a conductive layer for floating gates) can be formed, forexample, using polysilicon. The isolation regions B of the semiconductorsubstrate 101 are exposed by etching the conductive layer and the gateinsulating layer 103, formed in the isolation regions B, using theisolation hard mask pattern as an etch mask. Accordingly, the firstconductive layers 105 a remain on the active regions A of the selectiontransistor regions, and the second conductive layers 105 b remain on theactive regions A of the memory cell region.

Trenches are formed in the semiconductor substrate 101 by etching theexposed isolation regions B. An insulating layer having a sufficientthickness is formed over the semiconductor substrate 101, including thetrenches and the isolation hard mask pattern, to gap-fill the trenches.An oxide layer, for example, can be used as the insulating layer. Next,a surface of the insulating layer is polished by a polishing process.The polishing process can be performed, for example, using a chemicalmechanical polishing (CMP) method. The polishing process is stopped whenthe first and second conductive layers 105 a and 105 b are exposed.

The first and second isolation layers 107 a and 107 b, which fill theinside of the trenches and have the same height, are formed through aseries of the above processes. Furthermore, the gate insulating layer103 and the first conductive layers 105 a over the semiconductorsubstrate 101 disposed between adjacent first isolation layers 107 aremain at the same height as the first isolation layers 107 a, and thegate insulating layer 103 and the second conductive layers 105 b overthe semiconductor substrate 101 between adjacent second isolation layers107 b remain at the same height as the second isolation layers 107 b.

In the state in which the surface of the first and second isolationlayers 107 a and 107 b and the first and second conductive layers 105 aand 105 b are polished as described above, a first photoresist pattern109 is formed which covers the first isolation layers 107 a, but exposesthe second isolation layers 107 b. That is, the first photoresistpattern 109 is formed to cover the stack materials in the selectiontransistor regions, but to leave open (expose) the stack materials inthe memory cell region.

Referring to FIGS. 2 and 3B, the height of the second isolation layers107 b is lowered by an etch process using the first photoresist pattern(refer to 109 of FIG. 3A) as an etch barrier. Next, the firstphotoresist pattern (refer to 109 of FIG. 3A) is removed. Accordingly,the height of the second isolation layers 107 b becomes lower than thatof the first isolation layers 107 a, and the first isolation layers 107a maintain the same height as the first conductive layers 105 a. Theheight of the second isolation layers 107 b can be controllablydecreased (lowered) through control of the EFH. Here, the first andsecond isolation layers 107 a and 107 b are required to have a higherheight than the height of the gate insulating layer 103 in order toprevent a reduction in the characteristic of the flash memory device.

Referring to FIGS. 2 and 3C, a dielectric layer 111, a capping layer113, and a BARC layer 115 are stacked over the semiconductor substrate101, including the first and second isolation layers 107 a and 107 b andthe first and second conductive layers 105 a and 105 b. A secondphotoresist pattern 117 is formed to cover the BARC layer 115 formed inthe memory cell region, and to leave open (expose) the BARC layer 115formed in the selection transistor regions.

The dielectric layer 111 can have, for example, a stack structure of anoxide layer/a nitride layer/an oxide layer. The capping layer 113 can beformed, for example, using polysilicon. Here, the capping layer 113functions to protect the dielectric layer 111 formed in the memory cellregion from an etch process, and it may be used as the bottom of a wordline. The BARC layer 115 is formed using, for example, a mixtureincluding an organic matter and is formed to prevent diffused reflectionwhen an exposure process for forming the second photoresist pattern 117is performed, thereby improving the profile of the second photoresistpattern 117.

In the present disclosure, the dielectric layer 111, the capping layer113, and the BARC layer 115 in the selection transistor regions have auniform thickness because they are stacked on the surface of thesemiconductor substrate 101, including the first isolation layers 107 aand the first conductive layers 105 a, after it has been polished.

Referring to FIG. 2 and FIG. 3D, the BARC layer (refer to 115 of FIG.3C), the capping layer 113, and the dielectric layer 111 formed in theselection transistor regions are sequentially etched by an etch processusing the second photoresist pattern (refer to 117 of FIG. 3C) as anetch barrier. Next, the BARC layer (refer to 115 of FIG. 3C) and thesecond photoresist pattern (refer to 117 of FIG. 3C) which remain intactare removed. Accordingly, contact holes 120, which expose the firstconductive layers 105 a and the first isolation layers 107 a formed inthe selection transistor regions, are formed in the dielectric layer111.

When sequentially etching the BARC layer (refer to 115 of FIG. 3C), thecapping layer 113, and the dielectric layer 111 by the etch processusing the second photoresist pattern (refer to 117 of FIG. 3C), the etchprocess preferably is performed with a relative etch selectivity takeninto consideration. For example, when etching the BARC layer 115, anetch material preferably is used which has a high etch selectivity forthe BARC layer (refer to 115 of FIG. 3C) made of the mixture, forexample, including the organic matter, as compared to the capping layer113 made, for example, of polysilicon. Furthermore, when etching thecapping layer 113, an etch material preferably is used which has a highetch selectivity for the capping layer 113 formed, for example, ofpolysilicon as compared to the dielectric layer 111. An etch gasincluding a mixture of HBr gas and O₂ gas preferably is used as the etchmaterial having a high etch selectivity for the capping layer 113 formedof polysilicon as compared to the dielectric layer 111. Furthermore,when etching the dielectric layer 111, an etch material preferably isused which has a high etch selectivity for the dielectric layer 111 ascompared to the first conductive layers 105 a.

When performing the etch process using the second photoresist pattern(refer to 117 of FIG. 3C) as described above, the BARC layer (refer to115 of FIG. 3C), the capping layer (refer to 113 of FIG. 3C), and thedielectric layer 111 (i.e., etch targets) are formed to have a uniformthickness, thereby being capable of securing an etch margin. In moredetail, in the present disclosure, the etch targets (i.e., the BARClayer (refer to 115 of FIG. 3C), the capping layer (refer to 113 of FIG.3C), and the dielectric layer 111 formed in the selection transistorregions) are stacked over the first conductive layers 105 a and thefirst isolation layers 107 a. Accordingly, there are no steps in thestructure because the first conductive layers 105 a and the firstisolation layers 107 a have the same height. In other words, the BARClayer (refer to 115 of FIG. 3C), the capping layer (refer to 113 of FIG.3C), and the dielectric layer 111 can be uniformly formed in theselection transistor regions without steps. Consequently, whenperforming the etch process using the second photoresist pattern (referto 117 of FIG. 3C), the occurrence of an open failure can be preventedbecause the etch thickness can be easily set and the etch targets can beuniformly etched. Furthermore, since the second isolation layers 107 b(i.e., the etch targets) in the memory cell region are etched to have alower height than the first isolation layers 107 a in the selectiontransistor region, the distance between the first isolation layers 107 aand the gate insulating layer 103 is large as compared with the priorart. Accordingly, in the present disclosure, when etching the firstisolation layers 107 a in the selection transistor regions, damage tothe gate insulating layer 103 can be prevented and the etch thickness ofthe first isolation layers 107 a can be easily controlled.

After the first conductive layers 105 a are exposed by the etch processfor the dielectric layer 111, a process of recessing the firstconductive layers 105 a formed in the selection transistor regions canbe further performed so that a top surface of each of the firstconductive layers 105 a is made concave, as shown in FIG. 3D. In orderfor the top surface of the each of the first conductive layers 105 a tobecome concave, a recess process using, for example, a mixed etch gas ofHBr gas and N₂ gas may be performed, or a recess process may beperformed, for example, by lowering a bias power as compared with whenthe dielectric layer 111 and the capping layer 113 are etched. When thetop surface of each of the first conductive layers 105 a becomes concavethrough such a recess process, a contact area of the first conductivelayers 105 a and select lines formed in a subsequent process can beimproved, which can improve the contact resistance therebetween. Thefirst conductive layers 105 a formed in the selection transistor regionsmay have different surface forms according to conditions used in therecess process.

Referring to FIGS. 2 and 3E, after the first conductive layers 105 a andthe first isolation layers 107 a formed in the selection transistorregions are exposed, a process of removing the etch remnants isperformed using a cleaning process using, for example, a hydrofluoricacid (HF) solution. The height of the first isolation layers 107 abecomes lower than that of the first conductive layers 105 a by such acleaning process, thereby exposing the sidewalls of the first conductivelayers 105 a formed in the selection transistor regions. Accordingly, acontact area of the first conductive layers 105 a formed in theselection transistor regions and select lines formed in a subsequentprocess can be further improved, and so the contact resistancetherebetween can be further improved. Meanwhile, although the height ofthe first isolation layers 107 a becomes lower than that of the firstconductive layers 105 a through the cleaning process, it remains higherthan the height of the second isolation layers 107 b.

Referring to FIGS. 2 and 3F, a conductive layer 119 for control gates isdeposited in the selection transistor regions, including the firstconductive layers 105 a and the first isolation layers 107 a, and on thememory cell region including the dielectric layer 111. An etch processis performed so that the conductive layer 119 for control gates can bedivided on a line basis, thereby forming the select lines, including thesource select line SSL and the drain select line DSL, and the word linesWL.

The select lines are formed in the selection transistor regions so thatthey come in contact with the first conductive layers 105 a and thefirst isolation layers 107 a. Further, the word lines WL are formed onthe dielectric layer 111 remaining in the memory cell region.

Next, the first and second conductive layers 105 a and 105 b on theactive regions A and the dielectric layer 111 which have been leftexposed by the formation of the select lines and the word lines WL, areetched. Consequently, the dielectric layer 111 and the first and secondconductive layers 105 a and 105 b on the active regions A remain onlyunder the select lines and the word lines WL.

As described above, according to the present disclosure, when loweringthe height of the second isolation layers 107 b of the memory cellregion by controlling the EFH, the first isolation layers 107 a ofregions where the select lines will be formed have the same height asthe first conductive layers 105 a. Thus, in the process of forming thecontact holes in the dielectric layer 111, steps can be prevented fromoccurring between the first conductive layers 105 a and the firstisolation layers 107 a of regions where the select lines will be formed.Accordingly, the present disclosure can secure an etch margin becausethe thickness of layers (i.e., etch targets) can be uniformly formedwhen forming the contact holes. That is, in the etch process for formingthe contact holes in the dielectric layer 111, layers (i.e., etchtargets) have a uniform thickness and have no steps. Accordingly, theetch thickness of etch targets can be easily controlled, and the problemof an open failure can be prevented. Furthermore, in the etch processfor forming the contact holes in the dielectric layer 111, thedielectric layer 111 (i.e., an etch target) is formed to have a higherheight than a top surface of the isolation layers. Accordingly, sincethe dielectric layer 111 remains distant from the gate insulating layer103, the etch process can be performed without damaging the gateinsulating layer 103.

Furthermore, the present disclosure can improve the contact resistancebetween the select lines and the first conductive layers because acontact area of the select lines and the first conductive layers can bewidened by recessing a top surface of the first conductive layers 105 aof regions where the select lines will be formed.

FIGS. 4A to 4F are sectional views illustrating a peripheral regiondefined outside a memory cell region and selection transistor regions.Transistors constituting a circuit for driving the select transistorsand the memory cells are formed in the peripheral region.

Referring to FIG. 4A, when forming the first and second isolation layers107 a and 107 b described above with reference to FIGS. 2 and 3A, thirdisolation layers 107 c are formed in the peripheral regionsimultaneously with the first and second isolation layers 107 a and 107b. It will be understood that the term “third isolation layers 107 c”can refer to the isolation layer elements disposed in the peripheralregion. Furthermore, the gate insulating layer 103 and third conductivelayers 105 c are formed in the semiconductor substrate 101 between thethird isolation layers 107 c. It will be understood that the term “thirdconductive layers 105 c” can refer to the conductive layer elementsdisposed in the peripheral region. A method of forming the thirdisolation layers 107 c is identical to the method of forming the firstand second isolation layers 107 a and 107 b described above withreference to FIGS. 2 and 3A, and so the height of the third isolationlayers 107 c is equal to that of the first isolation layers 107 a andthe second isolation layers 107 b before etching.

The first photoresist pattern 109 described above with reference toFIGS. 2 and 3A is formed to further cover the third isolation layers 107c. That is, the first photoresist pattern 109 is formed to further coverstacks on the peripheral region.

Referring to FIG. 4B, when performing the etch process of the secondisolation layers 107 b described above with reference to FIGS. 2 and 3B,the peripheral region is covered with the first photoresist pattern(refer to 109 of FIG. 4A). Accordingly, although the height of thesecond isolation layers 107 b is decreased (lowered), the height of thethird isolation layers 107 c can remain intact. Consequently, the heightof the third isolation layers 107 c can remain higher than that of thesecond isolation layers 107 b in the same manner as the first isolationlayers 107 a.

As described above with reference to FIGS. 2 and 3B, the firstphotoresist pattern (refer to 109 of FIG. 4A) is removed.

Referring to FIG. 4C, when stacking the dielectric layer 111, thecapping layer 113, and the BARC layer 115 (described above withreference to FIGS. 2 and 3C), the dielectric layer 111, the cappinglayer 113, and the BARC layer 115 are also stacked over thesemiconductor substrate 101 of the peripheral region, including thethird isolation layers 107 c and the third conductive layers 105 c. Thesecond photoresist pattern 117 described above with reference to FIGS. 2and 3C is then formed. Here, the second photoresist pattern 117 isformed to leave open not only the BARC layer 115 formed in the selectiontransistor regions, but also the BARC layer 115 formed in the peripheralregion.

In the present disclosure, the dielectric layer 111, the capping layer113, and the BARC layer 115 on the peripheral region can be formed tohave a uniform thickness because the surface of the semiconductorsubstrate 101, including the third isolation layers 107 c and the thirdconductive layers 105 c, on which they are stacked, is flat.

Referring to FIG. 4D, in the etch process described above with referenceto FIGS. 2 and 3D, the BARC layer (refer to 115 of FIG. 4C), the cappinglayer (refer to 113 of FIG. 4C), and the dielectric layer (refer to 111of FIG. 4C) on the peripheral region are also etched. Thus, contactholes 130, which expose the third conductive layers 105 c and the thirdisolation layers 107 c formed in the peripheral region, are furtherformed in the dielectric layer 111 in the peripheral region.

Next, in the recess process of the first conductive layers 105 adescribed above with reference to FIGS. 2 and 3D, the third conductivelayers 105 c formed in the peripheral region are also recessedsimultaneously with the first conductive layers 105 a formed in theselection transistor regions. Thus, a top surface of each of the thirdconductive layers 105 c becomes concave.

Furthermore, in the cleaning process described above with reference toFIGS. 2 and 3D, the sidewalls of the third conductive layers 105 cformed in the peripheral region, together with the sidewalls of thefirst conductive layers 105 a formed in the selection transistor regionsare also exposed.

Referring to FIG. 4F, when forming the select lines and the word lines(described above with reference to FIGS. 2 and 3F), gate lines GL arealso formed in the peripheral region. As described above with referenceto FIGS. 2 and 3F, the conductive layer 119 for control gates may beused as the gate lines GL formed in the peripheral region.

As described above with reference to FIGS. 4A to 4F, when forming thecontact holes in the dielectric layer 111, the same process is appliedto the selection transistor regions and the peripheral region.Accordingly, a contact area of the conductive layer, including first,second, and third conductive layers 105 a, 105 b, and 105 c and theconductive layer 119 for control gate in the selection transistorregions and the peripheral region, respectively, can be improved at thesame time without additional processes.

According to this disclosure, in the process of forming the contactholes 120 in the dielectric layer 111, steps can be prevented fromoccurring between the first isolation layers 107 a and the firstconductive layers 105 a under the select lines. Accordingly, in the etchprocess for forming the contact holes 120 in the dielectric layer 111,the etch thickness of layers (i.e., etch targets) can be easilycontrolled and the problem of an open failure can be prevented becausethe thickness of the layers becomes uniform.

Furthermore, according to the present disclosure, since the secondisolation layers 107 b in the memory cell region are etched to have alower height than the first isolation layers 107 a formed in theselection transition regions, the dielectric layer 111 (i.e., an etchtarget) is formed over the first isolation layers 107 a under the selectlines. Accordingly, the distance between the dielectric layer 111 andthe gate insulating layer 103 (i.e., etch targets) can be increasedbecause the height of the first isolation layers 105 a under the selectlines is large. Accordingly, the present disclosure can prevent the gateinsulating layer 103 from being damaged when the etch process isperformed on the dielectric layer 111.

Furthermore, according to the present disclosure, the height of thefirst isolation layers 107 a under the select lines is higher than thatof the second isolation layers 107 b formed in the memory cell region.Thus, although part of the first isolation layers 105 a under the selectlines is lost in the process of recessing the first conductive layers105 a, the gate insulating layer 103 is not damaged. That is, in thepresent disclosure, although the process of recessing the firstconductive layers 105 a is performed in order to widen a contact area ofthe select lines and the first conductive layers 105 a, the height ofthe first isolation layers 107 a under the select lines has a marginenough to protect the gate insulating layer 103. Accordingly, accordingto the present disclosure, a process of improving the contact resistancebetween the select lines and the first conductive layers 105 a can bestably carried out.

While the present invention has now been described and exemplified withsome specificity, those skilled in the art will appreciate the variousmodifications, including variations, additions, and omissions that maybe made in what has been described. Accordingly, it is intended thatthese modifications also be encompassed by the present invention andthat the scope of the present invention be limited solely by thebroadest interpretation that lawfully can be accorded the appendedclaims.

1. A flash memory device, comprising: a semiconductor substratecomprising selection transistor regions and a memory cell region definedbetween the selection transistor regions; first isolation layers formedin the selection transistor regions; and second isolation layers formedin the memory cell region, wherein the second isolation layers have alower height than the first isolation layers.
 2. The flash memory deviceof claim 1, wherein the semiconductor substrate further comprises: aperipheral region, and third isolation layers formed in the peripheralregion and having a same height as the first isolation layers.
 3. Theflash memory device of claim 1, further comprising: a gate insulatinglayer and conductive layers stacked over the semiconductor substratebetween adjacent first isolation layers; and select lines configured tocome in contact with the conductive layers and the first isolationlayers.
 4. The flash memory device of claim 3, wherein the firstisolation layers and the second isolation layers have a higher heightthan the gate insulating layer.
 5. The flash memory device of claim 3,wherein a top surface of each of the conductive layers are recessed andconcave.
 6. The flash memory device of claim 3, wherein the firstisolation layers have a lower height than the conductive layers, and theselect lines are in contact with a top surface and sidewalls of thefirst conductive layers.
 7. The flash memory device of claim 1, wherein:the selection transistor regions comprise a source selection transistorregion and a drain selection transistor region, and the memory cellregion is defined between the source selection transistor region and thedrain selection transistor region.
 8. The flash memory device of claim1, wherein the first isolation layers and the second isolation layersare adjacent and coupled to each other.
 9. The flash memory device ofclaim 3, wherein the first isolation layer has a same height as theconductive layer.
 10. The flash memory device of claim 9, wherein a topsurface of each of the conductive layers is recessed and concave.